Power consumption and power management are issues that have been highly concerned ever since. As transistor counts continue to increase, coupled with reducing feature size, system complexities have being increasing as well. In portable devices, Internet of Things and memories and the like application fields, reducing system power consumption is becoming more and more important.
The most commonly used technology to reduce power consumption is to dynamically control power voltages and clock signals in a system on chip (SoC). When the system has not work load, a module for power management in the system may turn off the power voltage and/or the clock, such that the system enters a dormant state in which power consumption is low. However, if an interval or external event occurs and the system thus needs to perform a corresponding task, the system in the dormant state is waken up and corresponding power voltages and clock signals are started.
As the reduction of power consumption is critical in mobile and memory applications, the system on chip generally has a plurality of complicated voltage domains, and control power and clocks in various voltage domains in different ways.
In the aspect of management of power and clocks, it is very complicated and difficult to control power and clocks in different voltage domains. In most application scenarios, requests to enter and exit (that is, wake-up) the dormant state are initiated frequently. Even if some voltage domains are taking a procedure to enter the dormant state, the system may receive a wake-up request, and needs to restart as soon as possible to enter an operating state.
Therefore, the module for power management for implementing the method for power managements may control clock-gating, resets, clock sources, resources, signal isolations, power source and the like important signals when the system is in the operating state.
Some typical module for power managements implemented based on hardware control all the signals related to the power source. Such a module for power management is capable of quickly entering or exiting the dormant state, and has a small leakage loss. However, the module for power management needs to be configured with great caution, since the module for power management controls very important signals, for example, the clock signal, reset signal and power source signal. If there is a bug in the module for power management, it causes a critical failure of whole chip.
For better fault tolerance of the module for power management and for ease of modification and update of the system, in the prior art a module for power management implemented based on a processor has been proposed. This module for power management may modify turn-on and turn-off control of the power source by updating a firmware program in the memory of a central processing unit, with no need to modify the hardware structure of the module for power management.